UNIWILL L50II0 - 37GL50200-C0 - REV C, Serwisowe

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5
4
3
2
1
VCC SWITCH
L50II0 Schematics Rev:C
PAGE
CONTENT
1.
Cover Page
L50II0 REV:A P/N LIST
D
D
2.
System Block Diagram
PCB P/N
PCB ASSY P/N
3.
POWER BLOCK DIAGRAM
4.
GPIO & POWER CONSU
5.
YONAH CPU HOST & CPU Thermal Sensor
6.
CPU_POWER
7.
CLK GEN ICS9LPR310-CLK
8.
NB(1)_Host
9.
NB(2)_DMI/Configuation/PM
10.
NB(3)_VGA_TV_LVDS_PCIEx16* I/F
11.
NB(4)_DDR2 I/F
12.
NB(5)_POWER
13.
NB(6)_POWER
C
C
14.
DDR2 _SO-DIMM
15.
SB(1)_CPU/SATA/IDE/RTC/LPC/AZALIA
16.
SB(2)_PCI/GPIO/SMBUS/PM/DMI/USB/PCIEx1
17.
SB(3)_Power
18.
IEEE1394A & CARD READER
19.
LAN 10/100
20.
HDD/ODD/FAN/SMART PWR
21.
EC IT8510E
22.
LCD PWR / INVERT CONN / LVDS CONN/ROM
23.
MINI CARD & NEW CARD & 3G & BT
24.
Daughter BD CONN
B
B
25.
CRT CONN WITH PR8800
26.
+5V&+3V(MAX8734A)
27.
+CPU CORE(MAX8771)
28.
+1.5V&+1.8V(OZ813) & +2.5V(RT9173B)
29.
+1.05V(OZ818) & +1.2V(RT9173B) & +0.9V(RT9173B)
30.
+1.0V_VGA & +1.8V_VGA(OZ813)
31.
POWER ON SWITCH FUNC.
32.
Charger func.(TL594) & DC IN CON & BATTERY CONN
33
Every Ver. Histor
37GL50200-C0 PCB MAIN BD FOR L50II0 REV:C
82GL50200-C0 M/B ASSY FOR L50II0
A
A
Name of Part
Cover Page
Project
L50II0
Rev
C
Sheet
UNIWILL COMPUTER CORP.
1
/
33
Date:
Tuesday, April 25, 2006
ISSUED BY DC2
3255
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3
2
1
CLK GEN
ICS 925083
INTEL CPU
Yonah/Merom
Dual/Singal
D
D
CRT
FSB533/667
TV
S-OUT
North Bridge
DDR2 Channel A
DDR2 SO-
DIMM1
/
533/66
7
INTEL
945GM
DDR2 SO-DIMM2/533/667
14.318 MHz
DDR2 Channel B
14"~15"
LCD
DMI BUS
ODD
PATA I/F
C
C
MASTER
South Bridge
AZALIA I/F
SATA HDD
SATA I/F
INTEL
AUDIO CODEC
AZALIA
MODEM
MIC
EAR/SPDIF
PATA HDD
ICH7M
ALC880
PCI I/F
IEEE 1394/CardReader
LAN
OZ128T
PCI I/F
AMP
RTL8100CL
TPA6011A
1XPCI-EXPRESS
B
B
MINI CARD
NEW CARD
Wireless LAN
SPK-L
SPK-R
EC
USB
LPC BUS
VGA SENSOR
CPU SENSOR
SYS Temp
Thermistor
DDR Temp
Thermistor
SMART PWR
LCD CTRL
ITE 8510
ADM1032
ADM1032
USB
USB
USB
USB
PR8800
NEW-Card
BlueTooth
3G-WCDMA
Debug
PORT
PWR ON
CTRL
BIOS
FAN_CPU
K/B
LED
Touch PAD
CHARGER
BATTERY
SWITCH
A
A
Name of Part
BLOCK_DIAGRAM
Project
L50II0
Rev
C
Sheet
UNIWILL COMPUTER CORP.
2
33
/
Date:
Tuesday, April 25, 2006
3255
5
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4
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POWER BLOCK DIAGRAM
VIN
+1.8VS
ISL6224
RSS090N03
RT9173B
+0.9VS
VID0
VID1
VIN
D
D
VID2
VID3
SC451
RSS090N03
CPU_CORE
+1.8V
VID4
SI4362
VID5
AO4422
VIN
+5VA
POWER Sequence
RSS090N03
AO4422
+5VS
SI4835
+5V
+3VA,+5VA,+12VA
SC1404
C
C
PWRSW
+12VA
.
+3.3VS_ON
SI2301
+12VS
+5VS,+12VS
+3.3VS
.
+1.5VS_ON
1ms
VIN
+3.3VA
+1.5VS
+3.3VS
.
+1.05VS_ON
+2.5VS
.
+1.8V_DDR_ON
RSS090N03
AO4422
RT9173B
1ms
+1.8VS
+3.3V/
＞
0.9A
1ms
SI4835
+1.05VS
.
50ms
10ms
RSMRST#
.
1s
PWRBTN#
.
+5V_ON
B
B
5.8ms
+5V
VIN
+1.5VS/4.5A
+1.5V
40ms
+3.3V
+2.5V
ISL6225
.
RSS090N03
AO4422
+1.8V_ON
+1.8V
+1.05V
+1.5V
.
VIN
+1.05VS/4.5A
7ms
Vcore_ON
Vcore
.
110ms
RSS090N03
AO4422
+1.05V/1.8A
PWROK/VR_PWRGD
H_PWRGD
PCIRST#/PLTRST#
A
A
CPURST#
Name of Part
POWER DIAGRAM & SEQUENCE
.
EC Control Pin
Project
L50II0
Rev
C
Sheet
UNIWILL COMPUTER CORP.
3
/
33
Date:
Tuesday, April 25, 2006
3255
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ICH6-M
CPU
ITE8510E
ITE8510E
ITE8510E
TEMP(
℃
GPIO
CPU CORE(V)
ICC(mA)
W
TEMP(
℃
GPIO
GPIO
VCC
ICC(mA)
W
GPI0
BM_BUSY#
2.0G
1.525
35.7
54.3
69
GPCF0
RF_SW#
GPC0
PWROK
+3.3V
300
1
70
GP7
2.2G
1.525
37.5
57.1
70
GPCF1
SILENT#/
GPC1
BAT2_SMBCLK
GP8
GPI11
EC_EXTSMI#
2.26G
1.525
38.1
58.0
70
GPCF2
IR_PS2CLK1
GPC2
BAT2_SMBDAT
SMB_ALERT#
2.4G
1.525
39.3
59.8
71
GPCF3
IR_PS2DAT1
GPC3
SB_ALERT#1
GPI12
2.5G
1.525
40
61.0
72
GPCF4
TP_CLK
GPC4
SB_ALERT#2
D
D
GPI13
2.53G
1.525
40.4
61.5
72
CLOCK GENERATOR
GPCF5
TP_DATA
GPC5
TP_LED#
GPO18
PM_STPPCI_ICH#
2.6G
1.525
41.05
62.6
72
TEMP(
℃
GPCF6
MAIL#
GPC6
CHG_ON
VCC
ICC(mA)
W
GPO19
GPO20
GPO21
2.66G
1.525
43.35
66.1
74
GPCF7
BROWSER#
GPC7
SILENT_LED#
+3.3V
180
0.594
70
PM_STPCPU_ICH#
2.8G
1.525
44.86
68.4
75
GPI0
SCROLL#
ADC0
BAT_TEMP
TPM_EN
1.525
55.9
85.2
81
3.06G
GPI1
CAPS#
ADC1
ADAPTOR_I
GPO23
GPI2
NUM#
ADC2
DDR2_TEMP
GPIO24
GPI3
CHG_R_LED#
ADC3
VGA_TEMP
GPIO25
ALC880
GPI4
CHG_G_LED#
DAC0
BRIGHTADJ
GPIO26
SATA0_GP
TEMP(
℃
GPI5
SUSLED_LED#
DAC1
CHG_I
VCC
ICC(mA)
W
GPIO27
GPI6
DAC2
FAN_CTRL0
+3.3V(DVDD)
71
0.234
70
VOLMAX
MCHE
GPIO28
GPH0
+1.8V_DDR_ON
DAC3
NA
TEMP(
℃
GPIO29
PNLSW1
VCC
ICC(mA)
W
GPH1
+1.8V_ON
GPIO30
PNLSW2
+3.3V
108.19
0.357
GPH2
+1.05VS_ON
GPIO31
PNLSW0
+3.3VA
501.3
1.254
GPH3
+3.3VS_ON
GPIO32
PM_CLKRUN#
+2.5V
1390
2.502
GPH4
+5V_ON
70
GPIO33
+1.5V
33.4
0.084
TPA6011A4
GPH5
SET_V
GPIO34
+VCCP
10
0.018
TEMP(
℃
GPH6
+1.5VS_ON
VCC
ICC(mA)
W
+VCC_GMCH_CORE
266
0.452
GPH7
VCORE_ON
3.3V
30
0.099W
85
GPG4
TP_DISABLE
C
C
GPG5
LCDSW
GPG6
MUTE#
GPG7
EXTTS#0
ADM1032
GPB0
CELERON_VO_DET
TEMP(
℃
GPB1
CPPE#
VCC
ICC
W
GPB2
PM_RSMRST#
+3.3V
170uA
0.56mW
150
ICH6-M
GPB3
BAT_SMBCLK
TEMP(
℃
VCC
ICC(mA)
W
GPB4
BAT_SMBDAT
+3.3V
96
0.315
GPB5
H_A20GATE
+3.3VA
275
0.909
GPB6
H_RCIN#
+1.5V
487
0.876
GPB7
RFLED_ON#
70
+1.5VA
27
0.049
GPE0
NA
+3.3VA_RTC
0.003
0.00001
GPE1
CPU_BSEL0
GPE2
NA
GPE3
NA
GPE4
PWRSW
GPE5
LID#
GPE6
PCM#
B
B
GPE7
PM_SLP_S3#
GPD0
ADAP_IN
GPD1
REMOTE_ON#
GPD2
PCI_RST#/PLT_RST#
GPD3
EC_EXTSMI#
GPD4
PM_SLP_S4#
SMART POWER TABLE
GPD5
PM_THROTTLING#
GPD6
FAN_SPD#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCORE
+_mV
GPD7
EC_PREST#
0
0
0
0
0
0
0
1.5000
-0mV
GPA0
BTL_BEEP
0
0
0
0
0
0
1
1.4875
-2.5mV
GPA1
EC_VID1
0
0
0
0
0
1
0
1.4750
-5mV
GPA2
EC_VID2
0
0
0
0
1
0
0
1.4500
-50mV
GPA3
EC_VID3
0
0
0
1
0
0
0
1.4000
-100mV
GPA4
EC_VID4
0
0
1
0
0
0
0
1.3000
-200mV
GPA5
SMP1_EN#
0
1
0
0
0
0
0
1.1000
-400mV
GPA6
SMP2_EN#
1
0
0
0
0
0
0
1
0.7000
-800mV
GPA7
PWRBTN#
0
0
1
1
0
1
1.1625
0
0
1
0
0
0
1
0
0
1
0
0
1
0
A
A
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
1
1
0
1
0
0
0
1
1
0
1
Name of Part
GPIO & POWER CONSU
Project
L50II0
Rev
C
Sheet
UNIWILL COMPUTER CORP.
4
/
33
Date:
Tuesday, April 25, 2006
3255
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8
H_A#[31:3]
8
H_D#[63:0]
8
H_REQ#[4:0]
8
H_RS#[2:0]
CN15-1
H_A#3
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
H1
E2
G5
H5
F21
E1
F1
CN15-2
A{3}#
A{4}#
A{5}#
A{6}#
A{7}#
A{8}#
A{9}#
A{10}#
A{11}#
A{12}#
A{13}#
A{14}#
A{15}#
A{16}#
ADSTB{0}#
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
H_ADS#
8
H_A#4
H_D#0
H_D#32
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
H23
G22
J26
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
H_BNR#
8
D{0}#
D{1}#
D{2}#
D{3}#
D{4}#
D{5}#
D{6}#
D{7}#
D{8}#
D{9}#
D{10}#
D{11}#
D{12}#
D{13}#
D{14}#
D{15}#
DSTBN{0}#
DSTBP{0}#
DINV{0}#
D{32}#
D{33}#
D{34}#
D{35}#
D{36}#
D{37}#
D{38}#
D{39}#
D{40}#
D{41}#
D{42}#
D{43}#
D{44}#
D{45}#
D{46}#
D{47}#
DSTBN{2}#
DSTBP{2}#
DINV{2}#
H_A#5
H_D#1
H_D#33
H_D#34
H_BPRI#
8
H_A#6
H_D#2
H_A#7
H_D#3
H_D#35
H_DEFER#
8
H_A#8
H_D#4
H_D#36
H_DRDY#
8
H_A#9
H_D#5
H_D#37
H_DBSY#
8
H_A#10
H_D#6
H_D#38
H_A#11
H_D#7
H_D#39
H_BREQ#0
8
H_A#12
H_D#8
H_D#10
H_D#40
H_A#13
H_IERR#
H_D#9
H_D#41
D
D20
D
IERR#
H_A#14
H_D#42
B3
INIT#
H_INIT#
15
H_A#15
H_D#11
H_D#43
H_A#16
H_D#12
H_D#44
H4
B1
F3
F4
G3
G2
G6
E4
LOCK#
RESET#
RS{0}#
RS{1}#
RS{2}#
TRDY#
HIT#
HITM#
H_LOCK#
8
H_D#13
H_D#45
8
H_ADSTB#0
H_CPURST#
H_D#14
H_D#46
H_CPURST#
8
H_RS#0
H_D#15
H_D#47
H_REQ#0
H_RS#1
K3
H2
K2
J3
L5
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
A6
A5
C4
D5
C6
B4
A3
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
REQ{0}#
REQ{1}#
REQ{2}#
REQ{3}#
REQ{4}#
A{17}#
A{18}#
A{19}#
A{20}#
A{21}#
A{22}#
A{23}#
A{24}#
A{25}#
A{26}#
A{27}#
A{28}#
A{29}#
A{30}#
A{31}#
ADSTB{1}#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD{01}
RSVD{02}
RSVD{03}
RSVD{04}
RSVD{05}
RSVD{06}
RSVD{07}
RSVD{08}
RSVD{09}
RSVD{10}
8
H_DSTBN#0
H_DSTBN#2
8
H_REQ#1
H_RS#2
8
H_DSTBP#0
H_DSTBP#2
8
H_REQ#2
8
H_DINV#0
H_TRDY#
8
H_DINV#2
8
H_REQ#3
H_REQ#4
H_HIT#
8
H_D#16
H_D#48
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
M24
N25
M26
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
H_HITM#
8
D{16}#
D{17}#
D{18}#
D{19}#
D{20}#
D{21}#
D{22}#
D{23}#
D{24}#
D{25}#
D{26}#
D{27}#
D{28}#
D{29}#
D{30}#
D{31}#
DSTBN{1}#
DSTBP{1}#
DINV{1}#
D{48}#
D{49}#
D{50}#
D{51}#
D{52}#
D{53}#
D{54}#
D{55}#
D{56}#
D{57}#
D{58}#
D{59}#
D{60}#
D{61}#
D{62}#
D{63}#
DSTBN{3}#
DSTBP{3}#
DINV{3}#
COMP{0}
COMP{1}
COMP{2}
H_A#17
H_D#17
H_D#49
H_A#18
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
H_D#18
H_D#50
BPM{0}#
BPM{1}#
BPM{2}#
BPM{3}#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
H_A#19
H_D#19
H_D#51
H_A#20
H_D#20
H_D#52
H_A#21
H_D#21
H_D#53
H_A#22
H_D#22
H_D#54
H_A#23
H_PREQ#
H_D#23
H_D#55
H_A#24
H_TCK
H_D#24
H_D#56
H_A#25
H_TDI
H_D#25
H_D#57
H_TDO
H_A#26
H_D#26
H_D#58
H_TMS
H_A#27
H_D#27
H_D#59
+1.05V
H_A#28
H_TRST#
H_D#28
H_D#60
H_A#29
H_D#29
H_D#61
H_A#30
H_D#30
H_D#62
H_A#31
H_PROCHOT#
H_D#31
H_D#63
D21
A24
A25
PROCHOT#
THERMDA
THERMDC
H_THERMDA
R337
1K_1%
8
H_ADSTB#1
8
H_DSTBN#1
H_DSTBN#3
8
H_THERMDC
8
H_DSTBP#1
H_DSTBP#3
8
8
H_DINV#1
15
H_A20M#
H_DINV#3
8
C7
15
H_FERR#
THERMTRIP#
PM_THRMTRIP# 9,15
H_GTLREF
H_COMP0
R99
27.4R_1%
AD26
C
15
H_IGNNE#
C
GTLREF
PM_THRMTRIP# space 2:1
Layout note: 0.5" max length.
H_COMP1
R92
54.9R_1%
H_COMP2
R94
27.4R_1%
15
H_STPCLK#
H_COMP3
R333
2K_1%
R91
54.9R_1%
A22
A21
V1
15
H_INTR
BCLK{0}
BCLK{1}
CLK_CPU_BCLK
7
COMP{3}
R388
*1K
H_TEST1
C26
D25
15
H_NMI
CLK_CPU_BCLK#
7
TEST1
TEST2
15
H_SMI#
H_TEST2
MISC
R387
51R
E5
B5
D24
D6
D7
AE6
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PS1#
H_DPRSTP#
15,27
H_DPSLP#
15
T22
H_DPWR#
8
RSVD{12}
CPU_BSEL0
B22
B23
C21
BSEL{0}
BSEL{1}
BSEL{2}
H_PWRGD
15
CPU_BSEL1
9,21
CPU_BSEL1
H_CPUSLP#
8,15
CPU_BSEL2
D2
F6
D3
C1
AF1
D22
C23
C24
RSVD{13}
RSVD{14}
RSVD{15}
RSVD{16}
RSVD{17}
RSVD{18}
RSVD{19}
RSVD{20}
H_PSI#
27
I24075270
B25
RSVD{11}
+1.05V
I24074326
Close to NB
Design guide recommend 2.2K
R403
1K
CPU_BSEL0
9
CPU_BSEL0
R445
*10K
CLK_BSEL0
7
H_DPRSTP# Layout routing is
ICH-7 -> CPU -> IMVP-6 sequency
+1.05V
B
B
H_PREQ#
R82
*56R
+CPU_CORE
Close CPU
R170
100K
+1.05V
AUX_OFF#
26,32
Z0504
Q27
2N3904
H_IERR#
R404
56R
B
Design guide recommend 2.2K
H_PROCHOT#
R132
56R
C177
1u
CPU_BSEL1
PM_THRMTRIP#
R176
1K
Z0505
Q28
2N3904
H_STPCLK#
R131
150R
B
CPU_BSEL1
9,21
H_TDO
H_TMS
R252
10K
C176
0.1u
R84
*54.9R
CLK_BSEL1
7
R88
*39.2R
R402
1K
H_TDI
R90
150R
+3.3V
+3.3V
R408
200R
Z0503
H_CPURST#
R134
*54.9R
CPU Thermal Sensor
C447
1u/10V/Y5V/0603
Design guide recommend 2.2K
R154
100K
H_TRST#
H_TCK
R89
680R
CPU_BSEL2
R169
100K
CPU_BSEL2
9
R83
27.4R_1%
U15
R441
10K
Q21
2N7002
CLK_BSEL2
7
Z0506
G
A
H_THERMDA
A
2
7
SMBDAT_EC 7,21
D+
ADATA
R409
1K
C446
2200p/50V/X7R
C140
1u
H_THERM#
Q20
2N7002
4
8
SMBCLK_EC
7,21
THERM
SCLK
H_THERM#
R153
0R
Z0507
G
Name of Part
CPU_HOST
H_THERMDC
3
6
C165
*0.1u
D-
ALERT
BSEL2
BSEL1
0
BSEL0 MHZ
133
166
Project
Rev
L50II0
FSB533
0
1
ADM1032ARM
C
FSB667
0
1
1
Sheet
UNIWILL COMPUTER CORP.
5
/
33
Date:
Tuesday, April 25, 2006
3255
5
4
3
2
1
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